Leakage aware design post-processing

#The present invention broadly relates to the design of integrated circuits, particularly to the design of lithographic masks, and more particularly to improvements in creating targets for use in model-based optical proximity correction (MBOPC) or OPC Verification tools used in mask design processes.

#In the manufacture of integrated circuits, photolithographic processes are commonly used, in which a wafer is patterned by projecting radiation through a patterned mask to form an image pattern on a photo sensitive material, referred to as a photoresist, or simply resist. The exposed resist material is developed to form openings corresponding to the image pattern, and then the pattern is transferred to the wafer substrate by methods such as etching, as known in the art.

#The basic lithography system consists of a light source, a photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. The mask design process as described herein covers the steps from chip design, model-based optical proximity correction (OPC), OPC Verification and mask fabrication. Such mask design processes typically rely on accurate numerical models of the imaging processes, which are herein referred to as lithographic models, which provide predictions of the images produced by various lithographic processes, such as optical imaging and resist processes, as well as images resulting from other processes such as resist, etch and chemical-mechanical polish (CMP) process images.

#Referring to the exemplary drawings wherein like elements are numbered alike in the several figures, not necessarily drawn to scale, in which:

#FIG. 1 illustrates a flow chart of an embodiment of a method for designing an on-wafer target for use in an OPC or OPC verification tool in accordance with the invention.

#FIG. 2 illustrates a chip layout including three layers of device shapes.

#This invention presents a method for designing and optimizing a lithographic mask that accounts for lithographic process variations across the layout while meeting designers' intent for product requirements. The term “lithographic process” as used and referred to herein, includes, without limitation, any pattern transfer process, such as forming a resist image, forming implants, performing a patterned etch, etc. An integrated circuit design or chip design typically includes layouts of multiple layers of shapes to be printed. A device layer may be printed by using one or more lithographic masks. The on-wafer target is used by an OPC tool or OPC verification tool during the mask design process by ensuring or verifying that simulated image contours resulting from the mask (or masks) for printing a given layer matches the on-wafer target according to predetermined criteria. More particularly, the method, in accordance with the invention, modifies the initial design target by optimizing the on-wafer target used for optimizing a mask design in an OPC or OPC verification tool. The on-wafer target is modified to optimize an improvement in a device electrical metric, such as minimizing leakage current or power, subject to appropriate lithographic process, electrical or other yield constraints. The resulting optimized target is provided to a standard geometric-based MBOPC or OPC verification tool, and the resulting optimized mask will result in images that better meet the designers' intent than a standard OPC-optimized mask that is based on the original geometrically-designed target. A target optimized in accordance with the invention may also be provided to an ED-OPC tool, to increase the turn-around time of ED-OPC optimization.

#One embodiment of a method for designing an optimized target for use in a lithographic process tool, in accordance with the invention, is illustrated in FIG. 1. First, a chip layout of interest is provided (Block 110). The chip layout typically contains multiple layers of shapes, typically polygons, that, when printed, together form a predetermined number of JTotal devices the comprise the chip. Each device layer contains polygon shapes to be printed according to an image transfer process, generally referred to herein as a lithographic process.

#For example, referring to FIG. 2, the chip design 100 may contain a first layer having a shape 301 that represents a device active region to be formed in a substrate. A second layer includes shapes for gate conductor (e.g. polysilicon) lines 101, 102, 103, 104. The gate conductors 102, 103, when printed on the wafer, will form transistor devices 420, 430, respectively, where the gate conductors 102, 103 overlay the active region 301 along the length W. A typical value for W is about 600 nm. The width Lj of a jth polysilicon line is a critical dimension that determines the channel length of the device. A typical value for L is about 40 nm. The chip design 100 also includes a third layer containing a layout of contacts 201, 202, 203 and 204 for providing interconnection to other layers.