Method for verifying optical proximity correction

#The present application claims priority under 35 U.S.C 119(a) to Korean application number 10-2009-0059918, filed on Jul. 1, 2009, in the Korean intellectual property Office, which is incorporated herein by reference in its entirety set forth in full.

#Exemplary embodiments of the present invention relate generally to a method for fabricating a semiconductor device, and more particularly, to a method for verifying an optical proximity correction (OPC).

#Semiconductor memory devices, such as dynamic random access memory (DRAM), include a large number of fine patterns. Such fine patterns are formed through a photolithography process. According to the lithography process, a target film to be patterned is coated with a resist film, and a photomask in which circuit patterns to be transferred to a wafer are formed is disposed on the resist film. Then, the circuit patterns formed on the photomask are transferred to the resist film through an exposure process and a development process, thereby forming resist patterns partially exposing the surface of the target film. Subsequently, the exposed regions of the target film are removed by an etching process using the resist patterns as a mask, and the resist patterns are then stripped. In this manner, the fine patterns of the semiconductor memory device can be formed.

#The above and other aspects, features and other advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

#FIG. 1 is a flowchart for explaining a method for verifying an optical proximity correction according to an embodiment of the present invention;

#FIGS. 2 to 4 are diagrams for explaining a method for setting a verification range for detection of defects; and

#Hereinafter, embodiments of the present invention will be described with reference to accompanying drawings. However, the embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

#FIG. 1 is a flowchart for explaining a method for verifying an optical proximity correction according to an embodiment of the present invention. FIGS. 2 to 4 are diagrams for explaining a method for setting a verification range for detection of defects. FIG. 5 is a diagram showing an exposure defocus (ED) tree of a process window.

#Referring to FIG. 1, a method for verifying an optical proximity correction (OPC) according to an embodiment of the present invention is performed after step S100 of designing a target pattern layout to be transferred to a wafer. The target pattern layout is designed with a layout of patterns to be actually implemented on a wafer. The target patterns may be patterns applied to, for example, a DRAM device, a flash device, an SRAM device, and a logic device. Also, although the target pattern layout is not shown in the drawings, it may be formed by selecting one or more patterns from a group consisting of patterns such as line patterns, hole patterns, island patterns, and space patterns.