High density integrated circuitry for semiconductor memory having memory cells with a minimum capable photolithographic feature dimension

An integrated circuit comprising:

• a semiconductor die;
• at least 67,108,864 and no more than 68,000,000 functional and operably addressable memory cells arranged on the semiconductor die, the memory cells occupying a combined area on the semiconductor die that is no greater than 53 mm2, wherein each memory cell comprises at least one container-configured capacitor coupling to a word line formed substantially below the at least one container-configured capacitor, each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor;
• column addressing circuitry formed on the semiconductor die and coupled to the memory cells for addressing columns of the memory cells;
• and
• sense amplifier circuitry formed on the semiconductor die and coupled to the memory cells for sensing signals from rows of the memory cells,
• wherein the memory cells are formed with a minimum capable photolithographic feature dimension, a single one of the memory cells consuming an area of no more than six times the square of the minimum capable photolithographic feature dimension.