Dual damascene process
AssigneeUnited Microelectronics Corp.
InventorsShin-Chi Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Guang-Yaw Hwang
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AssigneeUnited Microelectronics Corp.
InventorsShin-Chi Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Guang-Yaw Hwang
Estimating the term…
A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
A dual damascene process, comprising:
Dependencies are inferred from the claim text.