Process for wet singulation using a dicing singulation structure

#1. Field of the Invention

#The present invention generally relates to a method for simultaneously dicing a plurality of chips on a wafer to achieve singulation (separation) of semiconductor chip products from parent wafers at the end of the wafer level fabrication process.

#2. Description of the Related Art

#The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of an exemplary embodiment of the invention with reference to the drawings, in which:

#FIG. 1 illustrates an example of a plurality of semiconductor chips fabricated on a single wafer;

#FIG. 2A illustrates an example of a first embodiment of the present invention;

#FIG. 1 illustrates an example of a plurality of semiconductor chips fabricated on a single wafer using a typical dicing blade of 50 μm. A semiconductor wafer 100 having a front side 102 and a backside 104 having a plurality of semiconductor chips (for example, at 106) fabricated thereupon. Each semiconductor chip has a series of fabricated components 108 (not shown in detail) and may have a top surface mount of ball electrodes 110 and bottom surface mounted ball electrodes 112 connected to the electronic components 108 via electrical conductors. A metal crackstop 114 and/or polysilicon crackstop 118 typically surrounds the semiconductor chip structure to protect the fabricated components 108 and the related electrical interconnections, 110, 112 from any cracks propagating from a die separation area 120 located between semiconductor chips, for example 106 and 118, during chip separation/singulation. A kerf area 122 is allocated between adjacent chips to accommodate material removed from the mechanical dicing blade typically having a width around 50 μm.

#This invention teaches the inclusion of a dicing crackstop or trench surrounding a chip that is intended for 3-D stacking, to be created and processed in such a way as to effect die singulation without requiring use of any mechanical cut (i.e. no saw or laser cut processing required). In addition to the obvious benefits with respect to elimination of potential mechanical (saw) damage, a dicing crackstop on the order of 5-10 μm wide would occupy a much reduced kerf footprint than would be required for a 50 μm blade width, allowing for a potential productivity improvement.

#FIGS. 2A-2F illustrate a first embodiment of the present invention including a semiconductor wafer 200 having a front side 202 and a backside 204 having a plurality of semiconductor chips (for example, at 206) fabricated thereupon. Each semiconductor chip has an active area including series of fabricated components 208 (not shown in detail) located in a layer extending across an upper portion of the wafer 200 which may further include a top surface mount electrodes. Bottom surface mounted electrodes 223 may be connected to the electronic components 208 via Through Silicon Vias (TSVs) 209 formed to provide electrical connections between the electrical components 208 and the backside of the wafer 204. TSV 209 may be formed in the wafer 200 prior to device 208 fabrication, after device fabrication but prior to on-chip interconnect fabrication, or after both device fabrication and on-chip interconnect fabrication. A metal crackstop 210 surrounds the active electronic components 208 to protect the active area once the semiconductor chips 206 have been separated by the below described singulation process. The above reference numbers for the first embodiment will be used for the remaining three embodiments of the invention for ease and consistency of reference.