Methods and systems for process compensation technique acceleration

A method for processing a semiconductor chip layout for fabrication, comprising:

• a) obtaining a chip layout having a number of cells placed in a section of the chip layout to form a prescribed integrated circuit;
• b) operating a computer to replace one or more of the number of placed cells with a corresponding process compensation technique (PCT) pre-processed cell, wherein a given PCT pre-processed cell represents a particular placed cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments within the given PCT pre-processed cell, wherein the cell-level-PCT processing operation of a given cell includes generation of at least one as-fabricated aerial image of one or more PCT processed levels of the given cell and evaluation of PCT processing adequacy based on the at least one as-fabricated aerial image;
• c) operating a computer to perform a chip-wide PCT processing operation on a given level of the chip layout to generate a chip-wide PCT processed chip layout for the given level;
• d) operating a computer to record the chip-wide PCT processed chip layout for the given level on a computer readable storage medium;
• and
• e) repeating operations c) and d) for each level of the chip that requires PCT processing for fabrication.

A process compensation technique (PCT) processing system, comprising:

• an input module defined to receive a chip layout for PCT processing, wherein the chip layout includes a number of cells placed in a section of the chip layout to form a prescribed integrated circuit;
• a cell substitution module defined to replace one or more of the number of cells in the chip layout with a corresponding PCT pre-processed cell, wherein a given PCT pre-processed cell represents a particular cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments within the given PCT pre-processed cell, wherein the cell-level-PCT processing operation of a given cell includes generation of at least one as-fabricated aerial image of one or more PCT processed levels of the given cell and evaluation of PCT processing adequacy based on the at least one as-fabricated aerial image;
• a PCT processing module defined to perform a chip-wide PCT processing operation on specified levels of the chip layout to generate a chip-wide PCT processed chip layout for each of the specified levels of the chip layout;
• and
• an output module defined to record the chip-wide PCT processed chip layout for each of the specified levels of the chip layout on a persistent storage medium.