High performance flash memory devices
AssigneeInternational Business Machines Corporation
InventorsDerek Chen, Huilong Zhu
Life of this patent
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Abstract
A flash memory device includes a wafer; a gate oxide layer disposed upon the wafer; a floating gate disposed upon the gate oxide layer, the wafer, or a combination thereof; the floating gate including a flat floating gate portion and a generally rectangular floating gate portion disposed upon selected areas of the flat floating gate portion; a high K dielectric material disposed upon the floating gate; and a control gate disposed upon the high K dielectric material; wherein the high K dielectric material forms a zigzag pattern coupling the floating gate with the control gate.
Claims20
A flash memory device comprising:
- a wafer;
- a gate oxide layer disposed upon the wafer;
- a floating gate disposed upon the gate oxide layer, the wafer, or a combination thereof;
- the floating gate comprising a continuous, flat floating gate portion and a plurality of generally rectangular floating gate portions disposed upon selected areas of the continuous, flat floating gate portion;
- a high K dielectric material disposed upon the floating gate;
- a control gate disposed upon the high K dielectric material;
- and
- a spacer disposed on side surfaces of the control gate, the high K dielectric material, and the floating gate, and the spacer disposed on a top surface of a buried oxide (BOX) layer;
- wherein the high K dielectric material forms a zigzag pattern coupling the floating gate with the control gate.
A method of manufacturing a flash memory device comprising:
- forming a gate oxide on a wafer;
- disposing a first floating gate layer on the wafer;
- disposing a second floating gate layer on the first floating gate layer;
- patterning a resist mask over the second floating gate layer;
- etching to remove at least a portion of the unprotected portions of the second floating gate layer, wherein the first floating gate layer remains substantially intact;
- wherein the etching defines a second floating gate layer having a plurality of generally rectangular shapes disposed upon the first floating gate layer, wherein the first floating gate layer is substantially flat;
- removing the resist mask;
- disposing a high K dielectric material on the second floating gate layer and the first floating gate layer;
- disposing a control gate layer on the high K dielectric material;
- and
- forming a spacer disposed on side surfaces of the control gate, the high K dielectric material, and the floating gate, and the spacer disposed on a top surface of a buried oxide (BOX) layer;
- wherein the high K dielectric material forms a zigzag pattern coupling the second floating gate layer and the first floating gate layer with the control gate layer.
Dependencies are inferred from the claim text.