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US 8,283,712 B2Granted
Semiconductor memory device and manufacturing method for semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorKeiichi Kushida
Life of this patent
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Abstract
A channel layer is deposited on a first impurity layer, a second impurity layer is deposited on the channel layer, a gate electrode is placed to surround a circumference of the channel layer with a gate insulating film interposed therebetween, a spin-injection magnetization-reversal element is deposited on the second impurity layer, a bit line is placed on the spin-injection magnetization-reversal element, and a word line is placed on the bit line to be electrically connected to the gate electrode.
Claims10
A semiconductor memory device comprising:
- a channel layer on a first impurity layer;
- a second impurity layer on the channel layer;
- a gate electrode around a circumference of the channel layer with a gate insulating film between the channel layer and the gate electrode;
- a spin-injection magnetization-reversal element on the second impurity layer;
- a bit line on the spin-injection magnetization-reversal element;
- a word line on the bit line configured to electrically connect to the gate electrode;
- and
- a magnetic shield layer around a circumference of the spin-injection magnetization-reversal element, the magnetic shield layer formed by extending the gate electrode around the circumference of the spin-injection magnetization-reversal element.
5 more elements
A semiconductor memory device comprising:
- a channel layer on a first impurity layer;
- a second impurity layer on the channel layer;
- a gate electrode around a circumference of the channel layer with a gate insulating film between the channel layer and the gate electrode;
- a spin-injection magnetization-reversal element on the second impurity layer, the spin-injection magnetization-reversal element comprising:
- a vertical-magnetization pinning layer,
- a first interface magnetic layer on the vertical-magnetization pinning layer,
- a tunnel film on the first interface magnetic layer,
- a second interface magnetic layer on the tunnel film, and
- a vertical-magnetization free layer on the second interface magnetic layer;
- a bit line on the spin-injection magnetization-reversal element;
- and
- a word line on the bit line configured to electrically connect to the gate electrode.
9 more elements
Dependencies are inferred from the claim text.