US 8,283,695 B2 · Devices with adjustable dual-polarity trigger- and holding-votage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated

Abstract

Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.

Claims15

Dependent claims

A semiconductor device comprising:

a substrate;
a first section formed in the substrate, the first section comprising:
a first forward blocking junction formed in a current path between a first electrode and a second electrode;
a first reverse blocking junction formed in a current path between the second electrode and an edge of the first section;
a second section formed in the substrate, the second section comprising:
a second forward blocking junction formed in a current path between a third electrode and a fourth electrode;
a second reverse blocking junction formed in a current path between the third electrode and an edge of the second section;
wherein the first electrode is connected to the fourth electrode, and wherein the second electrode is connected to the third electrode.

5 more elements

A semiconductor device comprising:

a substrate;
a first power rail connected to one of a ground or a negative voltage (Vs);
a second power rail connected to a circuit ground (VSS);
and a third power rail connected to positive voltage (VDD);
a first section formed in the substrate, the first section comprising:
a first forward blocking junction formed in a current path between a first electrode and a second electrode, wherein the current path between the first electrode and the second electrode comprises one of a P-N-P-N structure and an N-P-N-P structure;
a first reverse blocking junction formed in a current path between the second electrode and an edge of the first section;
an input/output pad,
wherein the first forward blocking junction and the first reverse blocking junction are provided to prevent conduction during operation ofthe-semiconcluctor device when the voltage on the input/output, pad raises above (VDD) or below (VS or VSS).

6 more elements

A semiconductor device comprising:

a substrate;
a first power rail connected to one of a ground or a negative voltage (VS);
a second power rail connected to a circuit ground (VSS);
and a third power rail connected to positive voltage (VDD);
a first section formed in the substrate, the first section comprising:
a first forward blocking junction formed in, a current path between a first electrode and a second electrode, wherein the current path between the first electrode and the second electrode comprises one of a P-N-P-N structure and an N-P-N-P structure;
a first reverse blocking junction formed in a current path between,the second electrode and an edge of the first section;
an input/output pad,
wherein the first forward blocking junction and the first reverse blocking junction are:
provided to prevent conduction during operation of the semiconductor device when the voltage on the input/output pad raises above (VDD) or below (VSor VSS).

7 more elements

Dependencies are inferred from the claim text.

Devices with adjustable dual-polarity trigger- and holding-votage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated

Life of this patent

Devices with adjustable dual-polarity trigger- and holding-votage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated

Life of this patent

Abstract

Claims15