US 8,276,031 B1 · Scan architecture for full custom blocks with improved scan latch

Abstract

A non-fighting fully clocked scan latch is described that is dynamically configurable to support both logic data latching and scan data latching. The described scan latch circuit design reduces a load placed on a logic data latch portion of the described circuit by a scan latch portion of the described circuit, and thereby increases the speed of the described scan latch to that of an output latch without scan capability. Power required to drive the described scan latch is reduced by clocking the circuit to avoid fighting and by reducing the number of transistors included in transistor stacks internal to the scan latch. By reducing drive power requirements, eliminating internal latch fighting, and increasing latch response, a versatile scan latch is achieved that may be successfully implemented in a wide range of circuits despite the use of different supply drive voltage, threshold voltage, source-to-drain voltage, and transistor technology combinations.

Claims20

Dependent claims

A scan latch comprising:

a logic data output storage circuit comprising:
a first transistor that controls a connection between a first data latch node of the logic data output storage circuit and a LOW logic signal source based on a slave phase clock signal of a two-phase clock;
and
a second transistor that controls a connection between a second data latch node of the logic data output storage circuit and the LOW logic signal source based on a scan clock signal, wherein no transistor stack within the logic data output storage circuit located between one of the first data latch node and a HIGH logic signal source, the first data latch node and the LOW logic signal source, the second data latch node and the HIGH logic signal source, the second data latch node and the LOW logic signal source, includes more than two transistors connected in series.

1 more element

A scan latch, comprising:

a first pair of transistors configured to isolate a first data latch node from a HIGH logic signal source and a LOW logic signal source based on a first clock phase of a slave phase clock signal of a two-phase clock;
a logic data pass-through switch configured to pass a logic data from a combinational logic circuit to the first data latch node based on the first clock phase of the slave phase clock signal of the two-phase clock;
and
a first transistor and one of the first pair configured to maintain the logic data stored at the first data latch node based on a second clock phase of the slave phase clock signal of the two-phase clock, a fixed value of a scan clock signal and a value of the logic data.

1 more element

Dependencies are inferred from the claim text.

Scan architecture for full custom blocks with improved scan latch

Life of this patent

Scan architecture for full custom blocks with improved scan latch

Life of this patent

Abstract

Claims20