Debug signaling in a multiple processor data processing system

A method comprising:

• clocking a first portion of debug circuitry using a first clock;
• clocking a second portion of debug circuitry using a second clock,
• wherein the first clock is asynchronous with respect to the second clock;
• transferring a first request to enter a debug mode from the first portion of debug circuitry to synchronization circuitry,
• wherein the first request to enter the debug mode is asynchronous with respect to the second clock;
• a first processor synchronizing the first request to enter the debug mode with the second clock to produce a first synced debug entry request;
• the first processor monitoring a second synced debug entry request being received from the second processor;
• and
• the first processor waiting to enter the debug mode until the first synced debug entry request and the second synced debug entry request are both asserted.

A method comprising:

• inputting a test clock to a first processor and to a second processor;
• inputting a first processor clock to the first processor;
• inputting a second processor clock to the second processor,
• wherein the test clock is asynchronous with respect to the first processor clock, and
• wherein the test clock is asynchronous with respect to the second processor clock;
• the first processor receiving a first request to enter a debug mode;
• the second processor receiving a second request to enter the debug mode,
• wherein the first request to enter the debug mode and the second request to enter the debug mode are synchronous with the test clock;
• the first processor synchronizing the first request to enter the debug mode with respect to the first processor clock to produce a first synced debug entry request;
• the second processor synchronizing the second request to enter the debug mode with respect to the second processor clock to produce a second synced debug entry request;
• the first processor receiving the second synced debug entry request from the second processor and using the second synced debug entry request to determine when to enter debug mode;
• and
• the second processor receiving the first synced debug entry request from the first processor and using the first synced debug entry request to determine when to enter debug mode.