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US 8,274,832 B2Granted
Dynamic polarization for reducing stress induced leakage current
AssigneeMicron Technology, Inc.
InventorsLuca Chiavarone, Mattia Robustelli, Angelo Visconti
Life of this patent
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Abstract
Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.
Claims21
A method comprising:
- operating a non-volatile memory device in a standby mode;
- and
- applying a voltage wave-form to a memory cell of said non-volatile memory device to generate an electric field between a floating gate of said memory cell and a substrate of said non-volatile memory device while storing a “0” state in said memory cell and while said non-volatile memory device is operating in said standby mode, wherein said “0” state corresponds to said floating gate being negatively charged.
A method comprising:
- operating a non-volatile memory device in a standby mode;
- applying a voltage wave-form to a memory cell of said non-volatile memory device to generate an electric field between a floating gate of said memory cell and a substrate of said non-volatile memory device while said non-volatile memory device is operating in said standby mode;
- and
- applying said voltage wave-form to a block of memory cells of said non-volatile memory device during said standby mode operation, wherein said voltage wave-form comprises a first amplitude portion having a first time span and a second amplitude portion having a second time span, and wherein said first and second time spans are based, at least in part, on a thickness of an oxide layer between said floating gate and said substrate.
1 more element
An apparatus comprising:
- a non-volatile memory cell array including a memory cell having a floating gate;
- and
- a controller to apply a voltage wave-form to said memory cell to generate an electric field between said floating gate and a substrate of said memory cell during a set state in said memory cell during a standby mode operation of said memory cell, wherein said set state corresponds to said floating gate being negatively charged.
An apparatus comprising:
- means for operating a non-volatile memory device in a standby mode;
- and
- means for applying a voltage wave-form to a memory cell of said non-volatile memory device to generate an electric field between a floating gate of said memory cell and a substrate of said non-volatile memory device to inhibit electrons on said floating gate from tunneling to said substrate while storing a “0” state in said memory cell and during said standby mode operation, wherein said “0” state corresponds to said floating gate being negatively charged.
Dependencies are inferred from the claim text.