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US 8,274,331 B2Granted
Differential receiver
AssigneeNanya Technology Corporation
InventorYu Meng Chuang
Life of this patent
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Abstract
A differential receiver includes a first amplifying circuit and a second amplifying circuit. The first amplifying circuit comprises a first differential pair of PMOS transistors, a first current source, and a first load resistance section, while the second amplifying circuit comprises a second differential pair of NMOS transistors, a second current source, and a second load resistance section. With the structure of the first and second amplifying circuits, an increased input common mode range can be obtained.
Claims13
A differential receiver, comprising:
- a first amplifying circuit comprising:
- a first differential pair of PMOS transistors configured to receive first and second input voltages;
- a first current source connected between a supply voltage source and the first differential pair of PMOS transistors;
- and
- a first load resistance section connected between a common node and the first differential pair of PMOS transistors, wherein nodes between the first differential pair of PMOS transistors and the first load resistance section serve as an output terminal and an inversion output terminal;
- and
- a second amplifying circuit comprising:
- a second differential pair of NMOS transistors configured to receive the first and second input voltages;
- a second current source connected between the common node and the second differential pair of NMOS transistors;
- and
- a second load resistance section connected between the supply voltage and the second differential pair of NMOS transistors, wherein nodes between the second differential pair of NMOS transistors and the second load resistance section are respectively connected to the output terminal and the inversion output terminal.
8 more elements
A differential receiver, comprising:
- a first amplifying circuit comprising:
- a first differential pair of PMOS transistors configured to receive first and second input voltages;
- a first current source connected between a supply voltage source and the first differential pair of PMOS transistors;
- a first load resistance section having an output terminal and an inversion output terminal both connected between a common node and the first differential pair of PMOS transistors;
- a second amplifying circuit comprising:
- a second differential pair of NMOS transistors configured to receive the first and second input voltages;
- a second current source connected between the common node and the second differential pair of NMOS transistors;
- and
- a second load resistance section having the output terminal and the inversion output terminal both connected between the supply voltage and the second differential pair of NMOS transistors;
- and
- a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is configured to provide a first bias voltage to the first amplifying circuit, and the second adjustment circuit is configured provide a second bias voltage to the second amplifying circuit;
- wherein the first adjustment circuit comprises:
- a first PMOS transistor having a source connected to the supply voltage, and having a gate configured to receive the first bias voltage;
- a second PMOS transistor having a source connected to a drain of the first PMOS transistor, and having a gate configured to receive the first input voltage;
- a load device having a first terminal connected to a drain of the second PMOS transistor and a second terminal connected to the common node;
- and
- an amplifier having a positive input terminal configured to receive the adjustable voltage, a negative input terminal connected to the first terminal of the load device, and an output terminal connected to the gate of the first PMOS transistor.
14 more elements
A differential receiver, comprising:
- a first amplifying circuit comprising:
- a first differential pair of PMOS transistors configured to receive first and second input voltages;
- a first current source connected between a supply voltage source and the first differential pair of PMOS transistors;
- a first load resistance section having an output terminal and an inversion output terminal both connected between a common node and the first differential pair of PMOS transistors;
- a second amplifying circuit comprising:
- a second differential pair of NMOS transistors configured to receive the first and second input voltages;
- a second current source connected between the common node and the second differential pair of NMOS transistors;
- and
- a second load resistance section having the output terminal and the inversion output terminal both connected between the supply voltage and the second differential pair of NMOS transistors;
- and
- a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit is configured to provide a first bias voltage to the first amplifying circuit, and the second adjustment circuit is configured provide a second bias voltage to the second amplifying circuit;
- wherein the second adjustment circuit comprises:
- a load device having a first terminal connected to the supply voltage source;
- a first NMOS transistor having a drain connected to a second terminal of the load device, and having a gate configured to receive the first input voltage;
- a second NMOS transistor having a drain connected to a source of the first NMOS transistor, having a gate configured to receive the second bias voltage, and having a source connected to the common node;
- and
- an amplifier having a positive input terminal configured to receive the adjustable voltage, a negative input terminal connected to the second terminal of the load device, and an output terminal connected to the gate of the second PMOS transistor.
14 more elements
Dependencies are inferred from the claim text.