Semiconductor memory device having pillar structures

A semiconductor memory device, comprising:

• rows and columns of active pillar structures comprising semiconductor material, each of the active pillar structures protruding from a surface of the device,
• wherein odd and even rows of the active pillar structures are alternately disposed in a first direction,
• odd and even columns of the active pillar structures are alternately disposed in a second direction,
• the odd rows and the even columns of the active pillar structures each consist of a plurality of first ones of the active pillar structures,
• the even rows and the odd columns of the active pillar structures each consist of a plurality of second ones of the active pillar structures, and
• the columns of the second active pillar structures are offset in the second direction from the columns of the first active pillar structures;
• buried bit lines each extending longitudinally in the first direction, and each of the buried bit lines electrically connected to the first pillar structures which make up one of the even columns of the active pillar structures and to the second active pillar structures which make up an adjacent one of the odd columns of the active pillar structures, and electrically connected to the first and second active pillar structures at lower portions thereof;
• first gate patterns each extending longitudinally in the second direction and respectively enclosing central portions of the first active pillar structures which make up one of the odd rows of the active pillar structures;
• and
• second gate patterns each extending longitudinally in the second direction and respectively enclosing central portions of the second active pillar structures which make up one of the even rows of the active pillar structures,
• wherein a width of each of the buried bit lines is substantially the same as or greater than a sum of a diameter of an upper portion of one of the first active pillar structures, a diameter of an upper portion of one of the second active pillar structures, and a distance between the adjacent even and odd columns of the active pillar structures made up of the first and second active pillar structures to which the buried bit line is electrically connected.

A semiconductor memory device, comprising:

• a plurality of active pillar structures comprising semiconductor material, the plurality of active pillar structures comprising first active pillar structures arranged in odd rows and even columns of the plurality of active pillar structures, and second active pillar structures arranged in even rows and odd columns of the plurality of active pillar structures, wherein the odd and even rows are alternately disposed in a first direction and the odd and even columns are alternately disposed in a second direction, and the odd columns of the second active pillar structures are offset in the second direction from the even columns of the first active pillar structures;
• buried bit lines each extending longitudinally in the first direction, the first pillar structures of one of the even columns and the second active pillar structures of an adjacent one of the odd columns protruding from a surface of each of the buried bit lines;
• first gate patterns extending longitudinally in the second direction, each first gate pattern enclosing a portion of each of the first active pillar structures in one of the odd rows;
• and
• second gate patterns each extending longitudinally in the second direction, each second gate pattern enclosing a portion of each of the second active pillar structures in one of the even rows,
• wherein the first gate patterns are spaced apart from adjacent second gate patterns in the first direction by intervals smaller than respective widths of the first gate patterns and respective widths of the second gate patterns.

A semiconductor memory device, comprising:

• a plurality of active pillar structures comprising semiconductor material, the plurality of active pillar structures comprising first active pillar structures arranged in odd rows and even columns of the plurality of active pillar structures, and second active pillar structures arranged in even rows and odd columns of the plurality of active pillar structures, wherein the odd and even rows are alternately disposed in a first direction and the odd and even columns are alternately disposed in a second direction, and the odd columns of the second active pillar structures are offset in the second direction from the even columns of the first active pillar structures;
• buried bit lines each extending longitudinally in the first direction, the first pillar structures of one of the even columns and the second active pillar structures of an adjacent one of the odd columns protruding from a surface of each of the buried bit lines;
• first gate patterns extending longitudinally in the second direction, each first gate pattern enclosing a portion of each of the first active pillar structures in one of the odd rows;
• and
• second gate patterns each extending longitudinally in the second direction, each second gate pattern enclosing a portion of each of the second active pillar structures in one of the even rows,
• wherein a width of each of the buried bit lines is substantially the same as or greater than a sum of a diameter of one of the first active pillar structures, a diameter of one of the second active pillar structures, and a distance between the even column of the one of the first active pillar structure and an adjacent odd column of the one of the second active pillar structure.