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US 8,274,080 B2Granted
Semiconductor wafer including guard ring patterns and process monitoring patterns
AssigneeSamsung Electronics Co., Ltd.
InventorDong-Hyun Han
Life of this patent
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Abstract
A semiconductor wafer includes semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns; and scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other.
Claims13
A semiconductor wafer, comprising:
- semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns;
- and
- scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other,
- wherein the process monitoring pattern includes:
- a first lower conductive layer,
- a first insulating layer on the first lower conductive laver,
- a first capping layer on the first insulating laver, the first capping layer including a denser insulating material than the first insulating layer, and
- a first upper conductive layer on the first capping layer, and
- wherein the outer guard ring patterns include:
- a second lower conductive layer being made of and merged with the first lower conductive layer,
- a second insulating layer on the second lower conductive layer, the second insulating layer being made of and merged with the first insulating layer,
- a second capping layer on the second insulating layer, the second capping layer being made of and merged with the first capping layer, and
- a second upper conductive layer on the second capping layer, the second upper conductive layer being made of and merged with the first upper conductive layer.
10 more elements
A semiconductor wafer, comprising:
- semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns;
- and
- scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other,
- wherein the process monitoring pattern includes a trench in the semiconductor substrate and a silicon oxide filler filling the trench.
1 more element
A semiconductor device, comprising:
- a semiconductor chip area having a semiconductor circuit pattern;
- an inner guard ring pattern disposed outside of the semiconductor circuit pattern;
- an outer guard ring pattern disposed outside of the inner guard ring pattern;
- and
- a process monitoring pattern disposed outside of the outer guard ring pattern, the outer guard ring pattern and the process monitoring pattern being merged with each other,
- wherein the process monitoring pattern includes:
- a first lower conductive layer,
- a first insulating layer on the first lower conductive layer,
- a first capping layer on the first insulating layer, the first capping layer including a denser insulating material than the first insulating layer, and
- a first upper conductive layer on the first capping layer, and
- wherein the outer guard ring pattern includes:
- a second lower conductive layer being made of and merged with the first lower conductive layer,
- a second insulating layer on the second lower conductive layer, the second insulating layer being made of and merged with the first insulating layer,
- a second capping layer on the second insulating layer, the second capping layer being made of and merged with the first capping layer, and
- a second upper conductive layer on the second capping layer, the second upper conductive layer being made of and merged with the first upper conductive layer.
12 more elements
A semiconductor device, comprising:
- a semiconductor circuit pattern disposed in a semiconductor chip area;
- an inner guard ring pattern surrounding the semiconductor circuit pattern;
- an outer guard ring pattern surrounding the inner guarding area;
- and
- a process monitoring pattern surrounding the outer guard ring pattern, the outer guard ring pattern and the process monitoring pattern being merged with each other, and the process monitoring pattern including a trench in the semiconductor substrate and a silicon oxide filler filling the trench.
2 more elements
Dependencies are inferred from the claim text.