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US 8,273,658 B2Granted
Integrated circuit arrangement including vias having two sections, and method for producing the same
AssigneeInfineon Technologies AG
InventorsKlaus Goller, Jakob Kriz
Life of this patent
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Abstract
An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.
Claims14
A method for producing an integrated circuit arrangement comprising:
- producing a first conductive structure;
- depositing at least one first dielectric layer after the production of the first conductive structure;
- depositing at least one hard mask layer after the deposition of the first dielectric layer;
- depositing at least one further dielectric layer after the deposition of the hard mask layer;
- patterning the further dielectric layer and of the hard mask layer by means of a photolithographic method in a first etching process with the production of a cutout in the further dielectric layer;
- patterning the first dielectric layer with the aid of the patterned hard mask layer in a second etching process, which differs from the first etching process, with the production of a cutout in the first dielectric layer;
- depositing a first metal layer at a first deposition temperature with the filling of the cutout in the first dielectric layer;
- after the deposition of the first metal layer, depositing a second metal layer at a second deposition temperature, which is lower than the first deposition temperature;
- and
- actively precooling the integrated circuit arrangement to the second deposition temperature prior to depositing the second metal layer.
7 more elements
A method for producing an integrated circuit comprising:
- fabricating an interconnect level comprising an interconnect;
- depositing a barrier layer over the interconnect level;
- depositing a first dielectric layer over the barrier layer;
- depositing a hard mask layer over the first dielectric layer;
- depositing a second dielectric layer over the hard mask layer;
- patterning the second dielectric layer using a photolithographic method in a first etching process to expose a portion of the hard mask layer;
- etching the exposed portion of the hard mask layer in a second etching process to expose a portion of the first dielectric layer;
- etching the exposed portion of the first dielectric layer based on the etched hard mask layer in a third etching process to expose the barrier layer and to provide a cutout in the first dielectric layer;
- etching the exposed portion of the barrier layer in a fourth etching process to expose the interconnect;
- depositing a first metal layer at a first deposition temperature over the exposed portions of the interconnect, the barrier layer, the first dielectric layer, the hard mask layer, and the second dielectric layer filling the cutout in the first dielectric layer;
- depositing a second metal layer over the first metal layer at a second deposition temperature that is lower than the first deposition temperature;
- and
- actively precooling the integrated circuit to the second deposition temperature prior to depositing the second metal layer.
10 more elements
Dependencies are inferred from the claim text.