Method to prevent surface decomposition of III-V compound semiconductors

A method of fabricating a semiconductor structure in which surface pitting of III-V semiconductor compounds is prevented, said method comprising:

• forming a silicon layer having a thickness from 70 Å to 380 Å directly on a surface of a III-V compound semiconductor, wherein a gate region including a protected photoresist mask is formed atop a portion of the silicon layer, said gate region further including a high k dielectric and an overlying gate conductor;
• removing exposed portions of the silicon layer not including the gate region;
• implanting source/drain dopants within exposed portions of the III-V compound semiconductor;
• and
• annealing at a temperature of about 800° C. or greater, wherein the surface pitting is limited to provide a surface roughness that is less than 250 nm and a root mean square roughness of less than 0.5 nm.