Patterning methodology for uniformity control

A method of fabricating a semiconductor device, comprising:

• forming a patternable layer over a substrate;
• forming a first layer over the patternable layer;
• forming a second layer over the first layer, the first and second layers having different material compositions and substantially different thicknesses;
• performing a first etching process to the second layer to form a plurality of second layer components, wherein at least a subset of the second layer components each define a critical dimension of the semiconductor device;
• performing a second etching process to the first layer to form a plurality of first layer components, wherein the second etching process is performed using the second layer components as etching masks;
• and
• performing a third etching process to the patternable layer, wherein the third etching process is performed using the first layer components as etching masks.

A method of fabricating a semiconductor device, comprising:

• forming a polysilicon layer over a substrate, the substrate having an amount of variation in topography;
• forming an anti-reflective layer over the polysilicon layer, the anti-reflective layer being multiple times thicker than the amount of variation in the topography of the substrate;
• forming a sacrificial layer over the anti-reflective layer, the sacrificial layer being substantially thinner than the anti-reflective layer;
• patterning the sacrificial layer to form a plurality of sacrificial features, wherein at least one of the sacrificial features has a width that is a function of a critical dimension of the semiconductor device;
• patterning the anti-reflective layer using the sacrificial features as masks;
• and
• thereafter patterning the polysilicon layer using the patterned anti-reflective layer.