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US 8,273,631 B2Granted
Method of fabricating n-channel metal-oxide semiconductor transistor
AssigneeUnited Microelectronics Corp.
InventorsI-Chang Wang, Ling-Chun Chou, Ming-Tsung Chen
Life of this patent
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Abstract
A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.
Claims11
A method of fabricating an n-channel metal-oxide-semiconductor transistor, comprising:
- providing a silicon substrate;
- forming a gate structure on the silicon substrate, the gate structure comprising:
- a gate insulation layer on the silicon substrate,
- a conductive layer on the gate insulation layer, and
- a spacer on a sidewall of the conductive layer;
- forming a source/drain region at each of two sides of the gate structure in the silicon substrate by introducing a dopant thereinto using the gate structure as a mask;
- performing an annealing process on the silicon substrate;
- performing an epitaxial process to form an epitaxial silicon layer covering the source/drain region and not covering the silicon substrate masked by the spacer;
- performing a plasma surface treatment on the epitaxial silicon layer to allow the epitaxial silicon layer to absorb a layer of fluorine ions on a surface thereof;
- forming a nickel layer covering the layer of fluorine ions and the epitaxial silicon layer;
- and
- performing a rapid thermal process to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.
9 more elements
A method of fabricating an n-channel metal-oxide-semiconductor transistor, comprising:
- providing a silicon substrate;
- forming a gate structure on the silicon substrate, the gate structure comprising:
- a gate insulation layer on the silicon substrate,
- a polysilicon layer on the gate insulation layer,
- a hard mask on the polysilicon layer, and
- a spacer on a sidewall of the polysilicon layer;
- forming a source/drain region at each of two sides of the gate structure in the silicon substrate by introducing a dopant thereinto using the gate structure as a mask;
- performing an annealing process on the silicon substrate;
- performing an epitaxial process to form an epitaxial silicon layer covering the source/drain region and not covering the silicon substrate masked by the gate structure;
- removing the hard mask on the polysilicon layer;
- performing a plasma surface treatment on the epitaxial silicon layer to allow the epitaxial silicon layer to absorb a layer of fluorine ions on a surface thereof;
- forming a nickel layer covering the layer of fluorine ions, the epitaxial silicon layer and the polysilicon layer;
- and
- performing a rapid thermal process to allow the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to react with the nickel layer thereabove, and the polysilicon layer to react with the nickel layer to form a nickel silicide layer.
11 more elements
A method of fabricating an n-channel metal-oxide-semiconductor transistor, comprising:
- providing a silicon substrate, the silicon substrate comprising:
- a patterned gate insulation layer on the silicon substrate,
- a patterned conductive layer on the patterned gate insulation layer,
- a first spacer on a sidewall of the patterned conductive layer,
- a second spacer on the first spacer,
- a lightly doped drain region formed on and in the silicon substrate by introducing a first dopant thereinto using the patterned conductive layer or the first spacer as a mask, and
- a source/drain region formed in the lightly doped drain region and the silicon substrate thereunder by introducing a second dopant thereinto using the patterned conductive layer, the first spacer and the second spacer as a mask;
- performing an annealing process on the silicon substrate;
- performing an epitaxial process to form an epitaxial silicon layer covering the source/drain region and not covering the silicon substrate masked by the spacer;
- performing a plasma surface treatment on the epitaxial silicon layer to allow the epitaxial silicon layer to absorb a layer of fluorine ions on a surface thereof;
- forming a nickel layer covering the layer of fluorine ions and the epitaxial silicon layer;
- and
- performing a rapid thermal process to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.
10 more elements
Dependencies are inferred from the claim text.