Semiconductor with a dynamic gate-drain capacitance
AssigneeInfineon Technologies Austria AG
InventorsAnton Mauder, Hans-Joachim Schulze, Carolin Tolksdorf, Winfried Kaindl, Armin Willmeroth
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AssigneeInfineon Technologies Austria AG
InventorsAnton Mauder, Hans-Joachim Schulze, Carolin Tolksdorf, Winfried Kaindl, Armin Willmeroth
Estimating the term…
A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
A method for manufacturing a semiconductor device, comprising:
A method for manufacturing a semiconductor device, comprising:
Dependencies are inferred from the claim text.