US 8,273,616 B2 · Gated-varactors

Abstract

Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.

Claims20

Dependent claims

A method of operating a semiconductor device that has a well over a substrate, and a gate region, a source region, and a drain region over the well, the method comprising:

forming a channel capacitor between a source region having a source voltage and a drain region having a drain voltage;
forming an oxide capacitor in the gate region having a gate voltage and a junction capacitor between the well and the source region or between the well and the drain region;
and
adjusting one or a combination of the drain voltage and the gate voltage to acquire a relationship between the drain voltage, the gate voltage, and total capacitance contributed by the junction capacitor, the channel capacitor, and the oxide capacitor.

1 more element

Dependencies are inferred from the claim text.

Gated-varactors

Life of this patent

Gated-varactors

Life of this patent

Abstract

Claims20