Protection of integrated circuit gates during metallization processes
AssigneeCypress Semiconductor Corporation
InventorsSanjay Rekhi, Nagendra Cherukupalli, Paul D. Keswick
Life of this patent
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Abstract
In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.
Claims12
A circuit for preventing charge buildup on an interconnect line during a metallization process, the circuit comprising:
- a first transistor, a drain of the first transistor being coupled to the interconnect line, a source of the first transistor being coupled to ground;
- and
- a capacitor coupling the gate of the first transistor to the interconnect line, the capacitor configured to switch ON the first transistor during the metallization process and protect a gate of a second transistor when charges accumulate on the interconnect line during a metallization process,
- wherein the interconnect line is on a first metal level and is coupled to ground on a topmost metal level through a plurality of vertically stacked vias, a second metal level and the topmost metal level over the first metal level to switch OFF the first transistor.
A circuit for preventing charge buildup on an interconnect line, the circuit comprising:
- a metal line;
- a first transistor including a drain coupled to the metal line and a source coupled to ground;
- and
- a capacitor coupling a polysilicon gate of the first transistor to the metal line, the capacitor being configured to switch ON the first transistor during a metallization process and protect a gate of the second transistor when charges accumulate on the interconnect line during the metallization process,
- wherein the capacitor is a parasitic capacitor formed by a portion of the metal line overlying the polysilicon gate of the first transistor.
A circuit comprising:
- a first transistor including a drain coupled through an interconnect line on a first metal level to a gate of a second transistor, a source coupled to ground, and a gate left floating;
- a capacitor coupled to the gate of the first transistor to the interconnect line, the capacitor configured to switch ON the first transistor during subsequent metallization processes and protect a gate of the second transistor when charges accumulate on the interconnect line during the metallization process;
- and
- a plurality of vertically stacked vias coupling the gate of the first transistor to ground at a topmost metal level to switch OFF the first transistor through at least a second metal level and the topmost metal level over the first metal level.
Dependencies are inferred from the claim text.