Release accumulative charges by tuning ESC voltages in via-etchers

A method of forming an integrated circuit structure, the method comprising:

• providing an etcher comprising an electrostatic chuck (ESC);
• placing a first wafer on the ESC;
• forming a first via opening in the first wafer using the etcher;
• after the step of forming the first via opening, applying a first reverse de-chuck voltage to the ESC to release the first wafer;
• placing a second wafer on the ESC;
• forming a second via opening in the second wafer using the etcher;
• and
• after the step of forming the second via opening, applying a second reverse de-chuck voltage to the ESC to release the second wafer, wherein the second reverse de-chuck voltage has a magnitude between about 50 percent and about 75 percent of a magnitude of the first reverse de-chuck voltage.

A method of forming an integrated circuit structure on a wafer, the method comprising:

• providing an etcher comprising an electrostatic chuck (ESC);
• placing the wafer on the ESC, wherein the wafer comprises:
• a conductive feature;
• and
• a dielectric layer over the conductive feature;
• etching the dielectric layer to form a via opening in the wafer using the etcher until the conductive feature is exposed through the via opening;
• after the step of forming the via opening, applying a first reverse de-chuck voltage to the ESC to release the wafer, wherein the first reverse de-chuck voltage is between about −650V and about −975V;
• etching an upper layer over the dielectric layer to form a trench opening;
• and
• after the step of forming the trench opening, applying a second reverse de-chuck voltage to the ESC to release the wafer, wherein the second reverse de-chuck voltage is lower than the first reverse de-chuck voltage.