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US 8,263,459 B2Granted
Method for forming a floating gate non-volatile memory cell
AssigneeImec
InventorPieter Blomme
Life of this patent
Estimating the term…
Abstract
Method for manufacturing a non-volatile memory comprising at least one array of memory cells on a substrate of a semiconductor material, the memory cells being self-aligned to and separated from each other by STI structures, the memory cells comprising a floating gate having an inverted-T shape in a cross section along the array of memory cells, wherein the inverted T shape is formed by oxidizing an upper part of the sidewalls of the floating gates thereby forming sacrificial oxide, and subsequently removing the sacrificial oxide simultaneously with further etching back the STI structures.
Claims16
A method of manufacturing a non-volatile memory, the method comprising:
- providing a semiconductor substrate;
- forming in the semiconductor substrate at least one Shallow Trench Isolation (STI) structure that extends into and above the semiconductor substrate in a height direction;
- forming on the semiconductor substrate an array of memory cells, each memory cell comprising a tunnel oxide layer formed on the semiconductor substrate, and a floating gate layer formed on the tunnel oxide layer, wherein adjacent memory cells in the array of memory cells are separated from one another by the at least one STI structure;
- partially etching back the at least one STI structure to expose an upper portion of the floating gate layer of each memory cell, wherein the exposed upper portion of each floating gate layer forms a fin with an exposed top and exposed sidewalls;
- oxidizing the exposed sidewalls of each fin;
- removing a first oxidized layer, thereby reducing the width of each fin, and forming an inverted-T floating gate from each floating gate layer;
- and
- oxidizing the exposed top of each fin, wherein removing the first oxidized layer additionally reduces the height of each fin.
5 more elements
A method of manufacturing a non-volatile memory, the method comprising:
- providing a semiconductor substrate;
- forming in the semiconductor substrate at least one Shallow Trench Isolation (STI) structure that extends into and above the semiconductor substrate in a height direction;
- forming on the semiconductor substrate an array of memory cells, each memory cell comprising a tunnel oxide layer formed on the semiconductor substrate, and a floating gate layer formed on the tunnel oxide layer, wherein adjacent memory cells in the array of memory cells are separated from one another by the at least one STI structure;
- partially etching back the at least one STI structure to expose an upper portion of the floating gate layer of each memory cell, wherein the exposed upper portion of each floating gate layer forms a fin with an exposed top and exposed sidewalls;
- oxidizing the exposed sidewalls of each fin;
- removing a first oxidized layer, thereby reducing the width of each fin, and forming an inverted-T floating gate from each floating gate layer;
- and
- implanting dopants to compensate for doping loss during oxidation.
5 more elements
A method of manufacturing a non-volatile memory, the method comprising:
- providing a semiconductor substrate;
- forming in the semiconductor substrate at least one Shallow Trench Isolation (STI) structure that extends into and above the semiconductor substrate in a height direction;
- forming on the semiconductor substrate an array of memory cells, each memory cell comprising a tunnel oxide layer formed on the semiconductor substrate, and a floating gate layer formed on the tunnel oxide layer, wherein adjacent memory cells in the array of memory cells are separated from one another by the at least one STI structure;
- partially etching back the at least one STI structure to expose an upper portion of the floating gate layer of each memory cell, wherein the exposed upper portion of each floating gate layer forms a fin with an exposed top and exposed sidewalls;
- oxidizing the exposed sidewalls of each fin;
- removing a first oxidized layer, thereby reducing the width of each fin, and forming an inverted-T floating gate from each floating gate layer;
- further oxidizing the exposed sidewalls of each fin;
- and
- removing a second oxidized layer, thereby further reducing the width of each fin.
6 more elements
A method of manufacturing a non-volatile memory, the method comprising:
- providing a semiconductor substrate;
- forming in the semiconductor substrate at least one Shallow Trench Isolation (STI) structure that extends into and above the semiconductor substrate in a height direction;
- forming on the semiconductor substrate an array of memory cells, each memory cell comprising a tunnel oxide layer formed on the semiconductor substrate, and a floating gate layer formed on the tunnel oxide layer, wherein adjacent memory cells in the array of memory cells are separated from one another by the at least one STI structure;
- partially etching back the at least one STI structure to expose an upper portion of the floating gate layer of each memory cell, wherein the exposed upper portion of each floating gate layer forms a fin with an exposed top and exposed sidewalls;
- oxidizing the exposed sidewalls of each fin;
- removing a first oxidized layer, thereby reducing the width of each fin, and forming an inverted-T floating gate from each floating gate layer;
- forming a hardmask layer on the exposed top of each fin;
- removing at least a portion of the hardmask layer;
- and
- etching the at least one STI structure while removing the at least a portion of the hardmask layer.
7 more elements
A method of manufacturing a non-volatile memory, the method comprising:
- providing a semiconductor substrate;
- forming in the semiconductor substrate at least one Shallow Trench Isolation (STI) structure that extends into and above the semiconductor substrate in a height direction;
- forming on the semiconductor substrate an array of memory cells, each memory cell comprising a tunnel oxide layer formed on the semiconductor substrate, and a floating gate layer formed on the tunnel oxide layer, wherein adjacent memory cells in the array of memory cells are separated from one another by the at least one STI structure;
- partially etching back the at least one STI structure to expose an upper portion of the floating gate layer of each memory cell, wherein the exposed upper portion of each floating gate layer forms a fin with an exposed top and exposed sidewalls;
- oxidizing the exposed sidewalls of each fin;
- removing a first oxidized layer, thereby reducing the width of each fin, and forming an inverted-T floating gate from each floating gate layer;
- forming a hardmask layer on the exposed top of each fin;
- further oxidizing the exposed sidewalls of each fin;
- and
- removing a second oxidized layer, thereby further reducing the width but not the height of each fin.
7 more elements
Dependencies are inferred from the claim text.