Method and apparatus for dividing clock frequencies
AssigneeXilinx, Inc.
InventorsXuewen Jiang, Adebabay M. Bekele
Life of this patent
Estimating the term…
Abstract
A method and apparatus for dividing clock frequencies are disclosed. For example, a circuit according to one embodiment of includes a high-speed divider and a plurality of programmable dividers cascading with the high-speed divider, wherein the plurality of programmable dividers are of a lower speed than the high-speed divider.
Claims18
A circuit, comprising:
- a high-speed divider;
- and
- a plurality of programmable dividers cascading with the high-speed divider,
- wherein the plurality of programmable dividers is of a lower speed than the high-speed divider, and
- wherein the high-speed divider comprises:
- a first input coupled to a source of a clock signal;
- a second input coupled to a first multiplexer;
- and
- an output coupled to a second multiplexer.
A method of dividing a frequency of a clock signal, the method comprising:
- dividing the frequency in a high-speed divider in accordance with a first divide-by mode, wherein the dividing in accordance with the first divide-by mode results in a new signal being produced by the high speed divider every n cycles of the clock signal;
- counting a number of times that the new signal is received in a primary programmable divider;
- counting a number of times that the new signal is received in a secondary programmable divider;
- and
- dividing the frequency in the high-speed divider in accordance with a second divide-by mode when the secondary programmable divider overflows,
- wherein the dividing in accordance with the second divide-by mode results in the new signal being produced by the high speed divider every m cycles of the clock signal, and wherein m is a different number than n.
A non-transitory computer-readable storage medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by a processor, cause the processor to perform steps of a method of dividing a frequency of a clock signal, comprising:
- dividing the frequency in a high-speed divider in accordance with a first divide-by mode, wherein the dividing in accordance with the first divide-by mode results in a new signal being produced by the high speed divider every n cycles of the clock signal;
- counting a number of times that the new signal is received in a primary programmable divider;
- counting a number of times that the new signal is received in a secondary programmable divider;
- and
- dividing the frequency in the high-speed divider in accordance with a second divide-by mode when the secondary programmable divider overflows, wherein the dividing in accordance with the second divide-by mode results in the new signal being produced by the high speed divider every m cycles of the clock signal, and wherein m is a different number than n.
Dependencies are inferred from the claim text.