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US 8,218,377 B2Granted
Fail-safe high speed level shifter for wide supply voltage range
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsAmit Tandon, Promod Kumar, Abhishek Lal
Life of this patent
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Abstract
A fail-safe level shifter switching with high speed and operational for a wide range of voltage supply includes a cascode module, and one or more speed enhancer modules. The cascode module receives one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.
Claims25
A circuit, comprising:
- a level shifting circuit including a first conduction path formed of a plurality of transistors connected in series between a first reference voltage terminal and a second reference voltage terminal, the first conduction path including a first internal node located at a first series connection point between two of the plurality of transistors in the first conduction path, the first conduction path further including a first output node located at a second series connection point between two of the plurality of transistors in the first conduction path, said level shifting circuit configured to level shift a first input signal received at a control terminal of one of the plurality of transistors to a level shifted output signal at the first output node;
- a first switching speed enhancing circuit configured to selectively couple the first internal node to a third reference voltage terminal in response to the first input signal.
A circuit comprising:
- a level shifting circuit including a first conduction path formed of a plurality of transistors connected in series between a first reference voltage terminal and a second reference voltage terminal, the first conduction path including a first internal node and a first output node and configured to be controlled for switching operation in response to a first input signal;
- a first switching speed enhancing circuit coupled between the first internal node and a third reference voltage terminal, the first speed enhancing circuit configured to selectively couple the first internal node to the third reference voltage terminal in response to the first input signal;
- and
- a second switching speed enhancing circuit coupled between the first output node and a fourth terminal, the second switching speed enhancing circuit configured to selectively couple the first output node to the fourth terminal in response to at least a complement of the first input signal.
1 more element
A circuit comprising:
- a cascode voltage level switching module comprising a series connection of the controlled conduction paths of a plurality of transistors, the series connection including an internal node between two of the plurality of transistors in said series connection;
- and
- at least one speed enhancer module configured to selectively couple said internal node of said series connection to a reference voltage node in response to an input signal also received by the cascade voltage level switching module so as to enable or enhance at least one of a charging or discharging of said internal node during switching of the cascode voltage level switching module.
A memory module, comprising:
- a storage array;
- and
- read and write logic incorporating at least one voltage level shifter;
- wherein the voltage level shifter comprises:
- a cascode switching module;
- and
- at least one speed enhancer module coupled to a node of said cascode switching module, said speed enhancer module acting to enable or enhance at least one a charging or discharging of said node during switching by the cascode switching module;
- wherein said speed enhancer module comprises a single controlled switch having one main terminal coupled to the node, its second main terminal coupled to a first voltage node and its control terminal coupled to an input signal node.
5 more elements
A memory module, comprising:
- a storage array;
- and
- read and write logic incorporating at least one voltage level shifter;
- wherein the voltage level shifter comprises:
- a cascode switching module;
- and
- at least one speed enhancer module coupled to a node of said cascode switching module, said speed enhancer module acting to enable or enhance at least one a charging or discharging of said node during switching by the cascode switching module;
- wherein said speed enhancer module comprises a pair of series-coupled controlled switches, a first one of the series-coupled controlled switches having its first main terminal coupled to the node, its second main terminal coupled to a first main terminal of a second one of the series-coupled controlled switches, a second main terminal of said second series-coupled controlled switch being coupled to a first voltage node, a control terminal of said first series-coupled controlled switch being coupled to an input signal node and a control terminal of said second series-coupled controlled switch being coupled to an output level shifted node of the cascade voltage level shifting module.
5 more elements
A circuit, comprising:
- a first plurality of first MOS transistors having source-drain paths connected in series between a first voltage reference node and a second voltage reference node, the series connection of said first MOS transistors including a first internal node and a first output node, said first MOS transistors including a first input transistor having a gate connected to receive an input signal, said first plurality of first MOS transistors configured to level shift said input signal and generate a level shifted signal at the first output node;
- and
- a first speed enhancing MOS transistor having a source-drain path coupled between said first internal node and a third voltage reference node, said first speed enhancing MOS transistor having a gate connected to receive said input signal.
Dependencies are inferred from the claim text.