Non-volatile memory low voltage and high speed erasure method

A non-volatile memory low voltage and high speed erasure method, said non-volatile memory comprising:

• a P-type well disposed in an N-type semiconductor substrate, a stacked gate structure disposed on said P-type well, a source and a drain disposed on two sides of said stacked gate structure and in said P-type well, said stacked gate structure includes at least a floating gate and a control gate disposed above said floating gate, said non-volatile memory erasure method includes following steps of:
• applying a substrate voltage Vsub, a P-type well voltage Vpwell, a source voltage Vs, a drain voltage Vd, and a control gate voltage Vc on said N-type semiconductor substrate, said P-type well, said source, said drain, and said control gate, when Vpwell is a ground voltage (=0), while satisfying following conditions:
• a. Vd>5V, Vs is close to or equal to 0;
• and
• b. Vd>Vc≧0, Vc decrementing with erasure time;
• and
• when Vpwell is a negative voltage, while satisfying following conditions:
• a. Vs is close to or equal to Vpwell;
• and
• b. Vd>Vc, Vc decrementing with erasure time.

A non-volatile memory low voltage and high speed erasure method, said non-volatile memory comprising:

• a stacked gate structure disposed on an N-type semiconductor substrate, a source and a drain disposed on two sides of said stacked gate structure and in said N-type semiconductor substrate, said stacked gate structure includes at least a floating gate and a control gate disposed above said floating gate, said non-volatile memory erasure method includes following steps of:
• applying a substrate voltage Vsub, a source voltage Vs, a drain voltage Vd, and a control gate voltage Vc on said N-type semiconductor substrate, said source, said drain, and said control gate, while satisfying following conditions:
• a. Vsub and Vs>5V;
• b. Vd is close to or equal to 0;
• and
• c. Vc>Vd, Vc incrementing with erasure time.

A non-volatile memory low voltage and high speed erasure method, said non-volatile memory comprising:

• an N-type well disposed in a P-type semiconductor substrate, a stacked gate structure disposed on said N-type well, a source and a drain disposed on two sides of said stacked gate structure and in said N-type well, said stacked gate structure includes at least a floating gate and a control gate disposed above said floating gate, said non-volatile memory erasure method includes following steps of:
• applying a substrate voltage Vsub, an N-type well voltage Vnwell, a source voltage Vs, a drain voltage Vd, and a control gate voltage Vc on said P-type semiconductor substrate, said N-type well, said source, said drain, and said control gate, while satisfying following conditions:
• a. Vnwell, and Vs>5V;
• b. Vnwell≧Vs;
• c. Vd is close to or equal to 0;
• and
• d. Vnwell≧Vc>Vd, Vc incrementing with erasure time.