ROM cell circuit for FinFET devices

A read only memory (ROM) cell array comprising:

• a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate;
• a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction;
• and
• a plurality of ROM cells for data storage and formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a Vss line and each cell of a second subset of ROM cells has a source electrically isolated, each of the plurality of ROM cells including at least two fin field-effect transistors (FinFETs) formed on respective fin active regions and respective cross-points of the fin active regions and the gates, and wherein:
• each of the plurality of ROM cells includes a first space between two adjacent intra-cell fin active regions and a second space between two adjacent inter-cell fin active regions, a ratio between the second space and the first space being greater than 1.5;
• and
• each of the FinFETs includes a gate electrically connected to a word line, and a drain electrically connected to a bit line.

A read only memory (ROM) cell array comprising:

• a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate;
• a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction;
• and
• a plurality of ROM cells for data storage and formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a Vss line, and each cell of a second subset of ROM cells has a source electrically isolated, and wherein each of the plurality of ROM cells includes:
• a first space between two adjacent intra-cell fin active regions and a second space between two adjacent inter-cell fin active regions, the ratio between the second space and the first space being greater than 1.5;
• and
• at least two fin field-effect transistors (FinFETs) formed on respective fin active regions and respective cross-points of the fin active regions and the gates, wherein drains of the at least two FinFETs are electrically connected by a silicide feature formed on a silicon epitaxy feature.