Logic circuit and semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsYutaka Shionoiri, Hidetomo Kobayashi
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Abstract
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
Claims26
A logic circuit including a first period during which a clock signal is input and a second period during which the clock signal is not input, comprising:
- a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period,
- wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×1019 (atoms/cm3) or lower, and
- wherein the oxide semiconductor comprises a crystal, a c-axis of which is in a direction perpendicular to a surface of the oxide semiconductor.
A logic circuit including a first period during which an enable signal is at a high level and a second period during which the enable signal is at a low level, comprising:
- an AND gate, wherein a first input terminal of the AND gate is electrically connected to an enable signal line, and a second input terminal of the AND gate is electrically connected to a clock signal line;
- and
- a flip-flop, wherein a first input terminal of the flip-flop is electrically connected to a data signal line, and a second input terminal of the flip-flop is electrically connected to an output terminal of the AND gate,
- wherein the flip-flop includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period,
- wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×1019 (atoms/cm3) or lower, and
- wherein the oxide semiconductor comprises a crystal, a c-axis of which is in a direction perpendicular to a surface of the oxide semiconductor.
A logic circuit including a first period during which an enable signal is at a low level and a second period during which the enable signal is at a high level, comprising:
- a NOR gate, wherein a first input terminal of the NOR gate is electrically connected to an enable signal line, and a second input terminal of the NOR gate is electrically connected to an inverted clock signal line;
- and
- a flip-flop, wherein a first input terminal of the flip-flop is electrically connected to a data signal line, and a second input terminal of the flip-flop is electrically connected to an output terminal of the NOR gate,
- wherein the flip-flop includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period,
- wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×1019 (atoms/cm3) or lower, and
- wherein the oxide semiconductor comprises a crystal, a c-axis of which is in a direction perpendicular to a surface of the oxide semiconductor.
A logic circuit including a first period during which an enable signal is at a high level and a second period during which the enable signal is at a low level, comprising:
- a latch, wherein a first input terminal of the latch is electrically connected to an enable signal line, and a second input terminal of the latch is electrically connected to an inverted clock signal line;
- and
- a flip-flop, wherein a first input terminal of the flip-flop is electrically connected to a data signal line, and a second input terminal of the flip-flop is electrically connected to an output terminal of the latch,
- wherein the flip-flop includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal,
- wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×1019 (atoms/cm3) or lower, and
- wherein the oxide semiconductor comprises a crystal, a c-axis of which is in a direction perpendicular to a surface of the oxide semiconductor.
Dependencies are inferred from the claim text.