Victim net crosstalk reduction

A circuit analysis tool, enabled with software instructions stored in a non-transitory computer-readable medium and executed by a processor, for minimizing circuit crosstalk exposure, the instructions comprising:

• providing a first circuit connected to an output node having a last gate with a plurality of inputs and an output;
• providing a second circuit having an output connected to the output node to supply an aggressor net delay range (A1) having a minimum delay (A1min) and a maximum delay (A1max), where the aggressor net delay range at least partially overlaps the victim net delay range;
• providing a third circuit having the output connected to the output node to supply an aggressor net delay range (A2) at least partially overlapping the victim net delay range and the aggressor net delay range (A1);
• calculating a first circuit victim net delay range having a minimum delay (Vmin) and a maximum delay (Vmax);
• adding a delay to a circuit selected from a group consisting of the second and third circuits, such that A1 does not overlap A2;
• minimizing crosstalk between the first circuit, and the second and third circuits, without an increase in the first circuit maximum signal delay.