Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency

A multithreading processor configured to concurrently execute a plurality of threads, comprising:

• an execution pipeline, for executing instructions of the plurality of threads, the execution pipeline configured for:
• generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline, whereby one or more instructions in the pipeline of the thread context associated with the thread context flush indicator can be flushed or nullified;
• and
• a skid buffer, coupled to the execution pipeline, configured for using the TC flush indicator to roll back the state of a number of instructions in the skid buffer, wherein the skid buffer is configured for re-issuing any flushed instructions of the number of instructions without having to re-fetch instructions from an instruction cache.