Method for optimizing an integrated circuit physical layout

A computer-implemented method of creating a global integrated circuit layout comprised of a number of polygons having a predetermined geometrical relation relative to each other, comprising:

• providing, by computer processor, an initial global integrated circuit layout wherein the global integrated circuit layout is provided by storing corner and edge coordinates of polygons representing the shapes of a local pattern;
• assessing local quality numbers, each as a function of the corner and edge coordinates of a local pattern of polygon shapes in said initial global integrated circuit layout;
• aggregating approximated functions of said local quality numbers, to derive an integral quality number associated to said initial global integrated circuit layout, wherein said approximated function is provided as linearly dependent on said corner and edge coordinates;
• perturbing said integral quality number by varying said corner and edge coordinates of said polygons in a global integrated circuit layout;
• and
• selecting perturbations of said corner and edge coordinates of said polygon shapes that improve the integral quality number, so as to optimize said global integrated circuit layout.