US 8,151,176 B2Granted

CPU instruction RAM parity error procedure

AssigneeLSI Corporation

InventorsGreg Tsutsui, Justin Jones

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Abstract

A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.

Claims15

Dependent claims

A parity checking circuit comprising:

a microprocessor;
instruction memory;
a parity checker;
an address capture device;
a data bus connected to the microprocessor, the instruction memory and the parity checker;
an address bus connected to the microprocessor, the instruction memory and the address capture device, wherein the instruction memory is configured to send a parity bit to the parity checker, wherein the address bus is configured to send an address to the parity checker, wherein the parity checker is configured to compare the address which the parity checker receives from the address bus to the parity bit which the parity checker receives from the instruction memory, and determine whether or not there is a parity error, wherein the parity checker is configured to send an error signal to the address capture device if a parity error is detected, wherein the address capture device is configured to capture an address that the address capture device receives from the address bus, whenever the address capture device receives the error signal from the parity checker.

3 more elements

Dependencies are inferred from the claim text.