US 8,151,175 B2 · Fault tolerant decoding method and apparatus

Abstract

A bit quality evaluator receives a sequence of bits. The bit sequence is provided to a decoding device that performs soft decision convolutional decoding on the sequence of bits. An off track event detector detects an occurrence of a trellis decode path change during the convolutional decoding operation and identifies a first symbol proximate corresponding to the occurrence of the trellis decode path change. An erasure decision circuit identifies at least the first symbol for erasure. The output of the first decoder and the erasure decision circuit are received at a second decoder, which decoder decodes the output of the first decoder after erasing at least the first symbol. The erasure decision circuit may also identify additional symbols for erasure using performance measures of the trellis decode path and using quality measures of the sequence of bits.

Claims12

Dependent claims

A method of electronic decoding comprising:

receiving, at a first decoding device, a data stream comprising a sequence of bits;
performing, using the first decoding device, convolutional decoding on the sequence of bits in the data stream;
identifying, using an off track event detector, an occurrence of a trellis decode path change during the convolutional decoding of the sequence of bits by the first decoder;
identifying, using the off track event detector, a first symbol proximate to the sequence of bits corresponding to the occurrence of the trellis decode path change;
identifying, using an erasure decision circuit, at least the first symbol for erasure;
receiving, at a second decoder, the output of the first decoder and the erasure decision circuit;
decoding, using a second decoding device, the output of the first decoder after erasing at least the first symbol;
and
outputting from the second decoding device decoded corrected data.

6 more elements

A decoding apparatus comprising:

a first decoding device configured for:
receiving a data stream comprising a sequence of bits;
and
performing convolutional decoding on the sequence of bits in the data stream;
an off track event detector configured for:
identifying an occurrence of a trellis decode path change during the convolutional decoding of the sequence of bits by the first decoder;
and
identifying a first symbol proximate to the sequence of bits corresponding to the occurrence of the treillis decode path change;
an erasure decision circuit configured for identifying at least the first symbol for erasure;
and
a second decoder configured for:
receiving the output of the first decoder and the erasure decision circuit;
decoding the output of the first decoder after erasing at least the first symbol;
and
outputting decoded corrected data.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/761,662Filed 12 Jun 2007 · continuation in part

Priority

5 Apr 2002

Published

US 2007/0234185 A14 Oct 2007

Granted

3 Apr 2012

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03M 13/2936
Using a block and a convolutional code: comprising an outer Reed-Solomon code and an inner convolutional code
H03M 13/3738
Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35: with judging correct…
H03M 13/4138
Using the Viterbi algorithm or Viterbi processors: soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
H03M 13/154
Using error location or error correction polynomials: error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial

Family

Application10/116,132Parent of this division · filed 5 Apr 2002

Application11/473,658Parent of this continuation-in-part · filed 23 Jun 2006

US 2007/0234185 A1Pre-grant publication · published 4 Oct 2007

US 7,549,106 B2Parent of this continuation-in-part

US 7,093,188 B2Parent of this division

Application11/473,658Parent of this division

US 2003/0192001 A1Published application

US 2006/0242547 A1Published application

US 8,151,175 B2This patent

From the US filing history. Foreign family members aren’t listed.

Fault tolerant decoding method and apparatus

Life of this patent

Fault tolerant decoding method and apparatus

Life of this patent

Abstract

Claims12