Adjustable error-correction for a reed solomon encoder/decoder
AssigneeLSI Corporation
InventorsAlan D. Poeppelman, Kevin T. Campbell
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AssigneeLSI Corporation
InventorsAlan D. Poeppelman, Kevin T. Campbell
Estimating the term…
Methods and structure described herein provide for reducing the overall delay of an RS encoder/decoder without changing the essential functionality of the RS encoder/decoder. In one embodiment, a cascade module reduces the combinatorial logical delay by reducing the total number of logical devices. In doing so, the cascade module couples encoder/decoder slices into blocks. A first block of the encoder/decoder slices is selectively operable in parallel with a second block of encoder/decoder slices. The number of encoder/decoder blocks is less than the overall number of encoder/decoder slices. The cascade module may also include a switch that selects encoder/decoder slices as needed, thereby providing for the implementation of the RS encoder/decoder with fewer logical devices.
An error correction system, comprising:
A method of providing error correction to data, the method comprising:
A method of correcting errors in received data and encoding transmit data with error correction, the method comprising:
A method of correcting errors in received data and encoding transmit data with error correction, the method comprising:
A transmitter for encoding data for transmission over a communication channel, the transmitter having an encoding system comprising:
A receiver for decoding received data from a communication channel, the receiver having an error correction system comprising:
Dependencies are inferred from the claim text.