Software programmable hardware state machines

A tangible computer readable storage medium comprising a processor embodied in software, the processor comprising:

• a programmable mask register;
• a decoder to decode each instruction in a sequence of instructions to generate decoded bits;
• an encoder coupled to the decoder and configured to selectively encode the decoded bits to produce values representing the sequence of instructions, wherein each value is smaller in size than an instruction that it represents;
• a buffer that stores the values representing the sequence of instructions;
• and
• control logic to determine whether there is a match between a sequence in the mask register and the sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action.

An instruction dispatch unit for a processor, comprising:

• a decoder to decode each instruction in a sequence of instructions to generate decoded bits;
• an encoder coupled to the decoder and configured to selectively encode the decoded bits to produce values representing instruction types being dispatched to an execution unit, wherein each value is smaller in size than an instruction that it represents;
• a buffer that stores the values representing instruction types being dispatched to an execution unit;
• a software accessible mask register enabled to store at least one sequence of values representing instruction types;
• and
• control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and to generate control signals to perform a desired action upon determining a match.

A method to prevent an unwanted change in the architectural state of a processor, the method comprising:

• storing a mask value in a programmable mask register;
• decoding each instruction in a sequence of instructions to generate decoded bits;
• encoding the decoded bits to produce values representing the sequence of instructions, wherein each value is smaller in size than an instruction that it represents;
• storing the values representing the sequence of instructions in a buffer;
• determining whether there is a match between the mask value in the mask register and the sequence in the buffer;
• and
• upon detecting a match, generating control signals to perform a desired action.

A method to detect a sequence of instructions that causes an error in a processor and to implement a solution, the method comprising:

• storing a mask value in a programmable mask register;
• decoding each instruction in a sequence of instructions being dispatched to an execution unit to generate decoded bits;
• encoding the decoded bits to produce values representing the sequence of instructions, wherein each value is smaller in size than an instruction that it represents;
• storing the values in an instruction type buffer;
• detecting an instruction to be dispatched to the execution unit whose execution will result in an error, based on a comparison between a mask in the mask register and a sequence of values in the instruction type buffer;
• and
• upon detecting the instruction, generating control signals to perform a desired action.

A system comprising:

• a decoder to decode each instruction in a sequence of instructions to generate decoded bits;
• an encoder coupled to the decoder and configured to selectively encode the decoded bits to produce values representing instruction types being dispatched to an execution unit, wherein each value is smaller in size than an instruction that it represents;
• a buffer that stores the values representing instruction types dispatched to an execution unit;
• a software accessible mask register enabled to store at least one sequence of values representing instruction types;
• and
• control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and to generate control signals to perform a desired action upon determining a match.

In an integrated circuit chip including a microprocessor, a method for preventing an unwanted condition caused by execution of a particular sequence of instructions, comprising:

• providing a first register configured to store a mask value;
• providing a circuit to decode each instruction in a sequence of instructions to generate decoded bits;
• providing a circuit to encode the decoded bits to produce values representing the sequence of instructions, wherein each value is smaller in size than an instruction that it represents;
• providing a second register configured to store the values representing the sequence of instructions;
• providing a circuit to compare values in the second register with the mask value stored in the first register and to produce a match indication when a particular sequence of instructions matches the mask value;
• and
• providing a circuit to generate control bits in response to the match indication, wherein the control bits cause the execution unit to perform a desired action.