Configuring routing in mesh networks

An apparatus, comprising:

• a plurality of processor cores;
• and
• an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions,
• the interconnection network being configurable to transmit data from an initial processor core or an input/output device to an intermediate processor core based on a first ordering policy of multiple ordering policies that specify an order of dimensions by which routing of data occurs over the interconnection network, with an order of dimensions that orders a first dimension before a second dimension indicating that data are to be routed along the first dimension followed by routing of data along the second dimension, and from the intermediate processor core to a destination processor core.

An apparatus, comprising:

• a processor comprising
• a plurality of processor tiles, each processor tile comprising a processor core, and
• a multi-dimensional interconnection network to interconnect the processor cores and enable transfer of data among the processor cores;
• and
• a memory controller having input/output ports that are coupled to corresponding input/output ports associated with some of the processor cores;
• the processor configured to route read data packets from the memory controller to one or more intermediate processor cores based on a first ordering policy of multiple ordering policies that specify an order of dimensions by which routing of data occurs over the interconnection network, with an order of dimensions that orders a first dimension before a second dimension indicating that data are to be routed along the first dimension followed by routing of data along the second dimension, and from the one or more intermediate processor cores to destination processor cores based on a second ordering policy of the multiple ordering policies, the read data packets from the memory controller each having a header specifying an address of an intermediate processor core;
• and
• the processor configured to route write data packets from one or more processor cores to one or more intermediate processor cores based on a third ordering policy of the multiple ordering policies, and from the one or more intermediate processor cores to the memory controller based on a fourth ordering policy of the multiple ordering policies, the write data packets from the processor cores each having a header specifying an address of an intermediate processor core.

A method, comprising:

• receiving a data packet at a first processor core, the data packet having a destination that corresponds to a second processor core, the first and second processor cores being part of an array of processor tiles, each processor tile comprising a processor core, with an intermediate processor core capable of determining a next intermediate processor core based on an ordering policy of multiple ordering policies that specify an order of dimensions by which routing of data occurs over the interconnection network, with an order of dimensions that orders a first dimension before a second dimension indicating that data are to be routed along the first dimension followed by routing of data along the second dimension;
• modifying a header of the data packet to specify an intermediate processor core;
• routing the data packet from the first processor core to the intermediate processor core through an interconnection network that interconnects the array of processor tiles;
• and
• routing the data packet from the intermediate processor core to the second processor core.