Dynamic address translation with frame management

A system for executing a perform a frame management function (PFMF) machine instruction in a computer system configured to translate a virtual address into a translated address of a block of main storage in a computer system of a machine architecture having a hierarchy of translation tables used for translation of said virtual address, said block of main storage having an associated storage key separate and distinct from any of said translation tables, said perform frame management function defined for said machine architecture, the system comprising:

• a computer memory configured to store machine instructions and a hierarchy of translation tables used for dynamic address translation of a virtual address into a real address or absolute address of said block of main storage, said real address being subject to a prefixing operation;
• and
• a processor in communication with said computer memory, said processor configured to interpret said machine instruction and accessing said hierarchy of translation tables stored in said memory, said processor performing a method comprising:
• a storage medium readable by said computer system, said computer readable medium storing instructions for performing:
• obtaining for execution the PFMF machine instruction defined for said architecture, the PFMF machine instruction comprising an opcode field, a first register field for identifying a first general register and a second register field for identifying a second general register;
• and
• executing the obtained PFMF machine instruction, the executing comprising:
• obtaining frame management information (FMI) from said first general register wherein said frame management information comprises a FMI key field comprising an FMI reference bit, an FMI change bit, and five FMI access-protection bits, the five access protection bits comprising four FMI access-control (ACC) bits and a FMI fetch protection bit;
• and
• responsive to a frame size code designating a large block of main storage, obtaining from said second general register, an operand absolute address of an initial sub-block of main storage within said large block of main storage, said large block of main storage consisting of an absolute addressed contiguous first plurality of sub-blocks of main storage, wherein each of said absolute addressed first plurality of sub-blocks of main storage has a corresponding storage key comprising a storage reference bit, a storage change bit and five of storage key access-protection bits, the five storage key access-protection bits comprising four storage access-control (ACC) bits and a storage fetch protection bit, wherein said storage access-control bits of the five storage key access-protection bits are usable for matching with program access-control bits of a program access key associated with a program request for storage access, the matching for determining whether a store operation to a corresponding sub-block of main storage is permitted to the corresponding sub-block of main storage, wherein the storage fetch protection bit is usable for determining whether a fetch operation from the corresponding sub-block of main storage is permitted, wherein the storage reference bit is usable for determining whether the corresponding sub-block of main storage has been accessed, and the storage change bit is usable for determining whether the corresponding sub-block of main storage has been stored to;
• and
• responsive to said frame size code designating said large block of main storage, setting one or more bits of said storage key of each corresponding storage key of each of a second plurality of said contiguous first plurality of sub-blocks of main storage with values of corresponding bits of said FMI key, said second plurality determined by said operand absolute address of said initial sub-block of main storage.

A computer implemented method for executing a perform frame management function (PFMF) machine instruction in a processor configured to translate a virtual address into a translated address of a block of main storage in a computer system of a machine architecture having a hierarchy of translation tables used for translation of said virtual address, said block of main storage having an associated storage key separate and distinct from any of said translation tables, said PFMF machine instruction defined for said machine architecture, the method comprising:

• obtaining for execution the PFMF machine instruction defined for said architecture, the PFMF machine instruction comprising an opcode field, a first register field for identifying a first general register and a second register field for identifying a second general register;
• and
• executing the obtained PFMF machine instruction, the executing comprising:
• obtaining frame management information (FMI) from said first general register wherein said frame management information comprises a FMI key field comprising an FMI reference bit, an FMI change bit, and five FMI access-protection bits, the five access protection bits comprising four FMI access-control (ACC) bits and a FMI fetch protection bit;
• and
• responsive to a frame size code designating a large block of main storage, obtaining from said second general register, an operand absolute address of an initial sub-block of main storage within said large block of main storage, said large block of main storage consisting of an absolute addressed contiguous first plurality of sub-blocks of main storage, wherein each of said absolute addressed first plurality of sub-blocks of main storage has a corresponding storage key comprising a storage reference bit, a storage change bit and five of storage key access-protection bits, the five storage key access-protection bits comprising four storage access-control (ACC) bits and a storage fetch protection bit, wherein said storage access-control bits of the five storage key access-protection bits are usable for matching with program access-control bits of a program access key associated with a program request for storage access, the matching for determining whether a store operation to a corresponding sub-block of main storage is permitted to the corresponding sub-block of main storage, wherein the storage fetch protection bit is usable for determining whether a fetch operation from the corresponding sub-block of main storage is permitted, wherein the storage reference bit is usable for determining whether the corresponding sub-block of main storage has been accessed, and the storage change bit is usable for determining whether the corresponding sub-block of main storage has been stored to;
• and
• responsive to said frame size code designating said large block of main storage, setting one or more bits of said storage key of each corresponding storage key of each of a second plurality of said contiguous first plurality of sub-blocks of main storage with values of corresponding bits of said FMI key, said second plurality determined by said operand absolute address of said initial sub-block of main storage.