Multiple access type memory and method of operation

A method for accessing a memory having a plurality of pipeline stages, the method comprising:

• receiving an initial address of an accessing sequence, wherein the initial address corresponds to a demand fetch;
• receiving a next address of the accessing sequence, wherein the next address corresponds to a speculative prefetch;
• providing data from the memory in response to the demand fetch, wherein, when data is being provided from the memory in response to the demand fetch, each pipeline stage of the plurality of pipeline stages is self-timed, independent of a system clock;
• providing data from the memory in response to the speculative prefetch, wherein, when data is being provided from the memory in response to the speculative prefetch, each pipeline stage of the plurality of pipeline stages is timed based on the system clock;
• receiving an asynchronous read signal with the initial address, wherein when the asynchronous read signal is received with the initial address, the asynchronous read signal is asserted to indicate that data corresponding to the initial address is to be accessed asynchronously to the system clock in response to the initial address corresponding to a demand fetch;
• and
• receiving the asynchronous read signal with the next address, wherein when the asynchronous read signal is received with the next address, the asynchronous read signal is negated to indicate that data corresponding to the next address is to be accessed synchronously to the system clock in response to the next address corresponding to a speculative prefetch.

A memory comprising:

• a plurality of pipeline stages, wherein the plurality of pipeline stages receives addresses corresponding to demand fetches and speculative prefetches at an input stage of the plurality of pipeline stages, and wherein the plurality of pipeline stages provides data corresponding to each of the demand fetches and speculative prefetches at an output stage of the plurality of pipeline stages;
• timing control circuitry coupled to receive a system clock, wherein, when data corresponding to each of the speculative prefetches is provided, each pipeline stage of the plurality of pipeline stages is timed based on the system clock, and when data corresponding to each of the demand fetches is provided, each pipeline stage of the plurality of pipeline stages is self-timed independent of the system clock;
• wherein the timing control circuitry is coupled to receive an asynchronous read signal that indicates whether data corresponding to an address received by the input stage of the plurality of pipeline stages is to be accessed asynchronously or synchronously to the system clock;
• and
• wherein the asynchronous read signal is asserted when an address corresponding to a demand fetch is received by the input stage, and the asynchronous read signal is negated when an address corresponding to a speculative prefetch is received by the input stage.