Method of increasing DDR memory bandwidth in DDR SDRAM modules

A memory apparatus comprising:

• a memory controller;
• at least one memory module that communicates with the memory controller and contains a plurality of double date rate (DDR) integrated circuit chips, each of said integrated circuit chips supporting page mode access, a bank activate command having associated therewith a row access strobe (RAS)-to-column access strobe (CAS) delay, a read command having associated therewith a CAS latency, and a precharge command having associated therewith a precharge latency;
• and firmware for high speed access, wherein the firmware for high-speed access includes:
• a CAS latency value for setting the CAS latency that is greater than a minimum CAS latency value supported by said integrated circuit chips at a selected frequency;
• and
• a RAS-to-CAS delay value and a precharge latency value for setting the RAS to CAS delay and the precharge latency, respectively, at least one of the RAS-to-CAS delay value and the precharge latency value being set lower than the set CAS latency value to minimize access times of consecutive accesses in which a subsequent access is out-of-page from an immediately previous access, such that the firmware specifies minimal numbers of penalty cycles from:
• said precharge command until a first page where the immediately previous access occurred is closed;
• and said bank activate command until a second page different than the first page is opened to access data within said second page using the read command.