Predicting parasitic capacitance in schematic circuit simulations using sub-circuit modeling

A computer-implemented method of determining parasitic capacitance for a transistor structure within an integrated circuit, the method comprising:

• defining a first expression to be C2Di=A2i+B2i/L+C2i/(L2), wherein C2Di represents a two-dimensional parasitic capacitance, wherein A2i, B2i, and C2i are fitting coefficients determined by fitting a first line to a first plurality of parasitic capacitances generated from a plurality of two-dimensional transistor structures, and L represents transistor channel length of a plurality of two-dimensional transistor structures;
• storing the first expression;
• storing a second expression that determines parasitic capacitance for transistor structures, wherein the second expression comprises the first expression and depends upon number of contacts of the transistor structures;
• receiving an input specifying a number of contacts for transistor structures used within a circuit design;
• calculating, using a processor, a value of parasitic capacitance for transistor structures using the second expression;
• and
• outputting the value of parasitic capacitance.

A computer program product comprising:

• a non-transitory computer-usable medium comprising computer-usable program code that determines parasitic capacitance for a transistor structure within an integrated circuit, the computer-usable medium comprising:
• defining a first expression to be C2Di=A2i+B2i/L+C2i/(L2), wherein C2Di represents a two-dimensional parasitic capacitance, wherein A2i, B2i, and C2i are fitting coefficients determined by fitting a first line to a first plurality of parasitic capacitances generated from a plurality of two-dimensional transistor structures, and L represents transistor channel length of a plurality of two-dimensional transistor structures:
• computer-usable program code that stores the first expression;
• computer-usable program code that stores a second expression that determines parasitic capacitance for transistor structures, wherein the second expression comprises the first expression and depends upon number of contacts of the transistor structures;
• computer-usable program code that receives an input specifying a number of contacts for transistor structures used within a circuit design;
• computer-usable program code that calculates a value of parasitic capacitance for transistor structures using the second expression;
• and
• computer-usable program code that outputs the value of parasitic capacitance.