System and method for implementing a phase detector to support a data transmission procedure

A phase detector for use in a data transmission procedure, comprising:

• a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether a clock signal received through a feedback loop is early or late with respect to input data;
• and
• a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in said input data, said phase detector generating a binary clock-control output signal corresponding to a current state of said lead/lag indicator signal T if said edge detection signal P is active, said binary clock-control output signal being filtered and applied directly to a clock generator device for adjusting said clock signal, said phase detector including an input circuit, said lead/lag indicator circuit, said positive-edge detector circuit, and an up/down selector circuit, said input circuit including a D flip-flop A, a first inverter, and a D flip-flop B, said first inverter being connected to a clock input of said D flip-flop B, said lead/lag indicator circuit including a D flip-flop D with a data input connected to an output of said D flip-flop B said lead/lag indicator circuit also including a clock input connected to an output of said D flip-flop A, said positive-edge detector circuit including a D flip-flop C with a data input connected to an output of said D flip-flop A, said positive-edge detector circuit also including a second inverter positioned between an output of said D flip-flop C and a first input of an edge-detector gate A, said up/down selector circuit including an up gate B with a first input connected to an output of said edge-detector gate A, a third inverter, and a down gate C with a first input connected to said output of said edge-detector gate A, said third inverter being positioned between an output of said D flip-flop D and a second input of said down gate C.