Signaling with superimposed clock and data signals

A data receiver circuit, comprising:

• an interface to receive an input signal that comprises a data signal and a clock signal superimposed on the data signal, wherein the data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate, and wherein the clock signal has a frequency N times the associated symbol rate, where N is an integer;
• a phase-locked loop (PLL) coupled to the interface to extract the clock signal from the input signal to provide an extracted clock signal by downconverting the input signal to an intermediate frequency signal, bandpass filtering the intermediate frequency signal to provide a filtered intermediate frequency signal, and downconverting the filtered intermediate frequency signal to produce a VCO control signal;
• a phase interpolator to adjust the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal;
• and
• a sampling circuit, synchronized to the phase-adjusted extracted clock signal, to sample the data signal at a sampling point.

A method of receiving data, comprising:

• receiving, at an interface, an input signal that comprises a data signal and a clock signal superimposed on the data signal, wherein the data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate, and wherein the clock signal has a frequency N times the associated symbol rate, where N is an integer;
• extracting the clock signal from the input signal to provide an extracted clock signal;
• adjusting the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal;
• and
• sampling the data signal at a sampling point, synchronized to the phase-adjusted extracted clock signal.

A computer readable medium containing circuit description data that, when operated on by a circuit compiler program being executed by a processor, synthesizes a data receiver circuit that includes:

• an interface to receive an input signal that comprises a data signal and a clock signal superimposed on the data signal, wherein the data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate, and wherein the clock signal has a frequency N times the associated symbol rate, where N is an integer;
• a phase-locked loop (PLL) coupled to the interface to extract the clock signal from the input signal to provide an extracted clock signal;
• a phase interpolator to adjust the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal;
• and
• a sampling circuit to sample the data signal at a sampling point, synchronized to the phase-adjusted extracted clock signal.

A data receiver circuit, comprising:

• means for receiving, at an interface, an input signal that comprises a data signal and a clock signal superimposed on the data signal, wherein the data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate, and wherein the clock signal has a frequency N times the associated symbol rate, where N is an integer;
• means for extracting the clock signal from the input signal to provide an extracted clock signal;
• means for adjusting the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal;
• and
• means for sampling the data signal at a sampling point, synchronized to the phase-adjusted extracted clock signal.

A data receiver circuit, comprising:

• means for receiving, at an interface, an input signal that comprises a data signal and a clock signal superimposed on the data signal, wherein the data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate, and wherein the clock signal has a frequency N times the associated symbol rate, where N is an integer;
• means for extracting the clock signal from the input signal to provide an extracted clock signal, including means for downconverting the input signal to an intermediate frequency (IF) signal, means for bandpass filtering the IF signal to provide a filtered IF signal, and means for downconverting the filtered IF signal to produce an oscillator control signal;
• means for adjusting the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal;
• and
• means for sampling the data signal at a sampling point, synchronized to the phase-adjusted extracted clock signal.