Packet acquisition controller with signal strength threshold control for wireless MIMO receiver

A packet acquisition controller coupled to an AGC controller and a packet detector;

• said AGC controller generating a gain control voltage for a particular RF front end coupled to an associated analog to digital converter (ADC), said ADC output forming an RX_IQ signal which is also coupled to said AGC controller, said AGC controller also generating an associated GT_NFLR signal when said input signal is greater than the noise floor by an increment delta;
• said packet detector generating a packet detect output from a stream of input data unless a PD_RESET input is asserted, said packet detector having an SNR_MODE input derived from said GT_NFLR signal, said SNR_MODE input increasing the number of signal input averages used to perform a packet detection, said packet detector generating an output by comparing a signal accumulator to a signal plus noise accumulator, said signal accumulator coupled to a signal correlator for each stream, said signal correlator providing a correlation of a delayed said stream with a conjugated said stream, said signal plus noise accumulator coupled to a noise correlator for each said stream, said noise correlator providing a correlation of said stream with a conjugated said stream, each said signal correlator and each said noise correlator having an associated weighting coefficient;
• said weighting coefficients set to 1 for said streams with said GT_NFLR asserted and said weighting coefficients set to 0 for said streams with said GT_NFLR not asserted.

A packet acquisition processor receiving a plurality of streams of IQ receiver data, the packet acquisition processor having:

• a packet detector coupled to each said stream of IQ receiver data, said packet detector generating a packet detect output when a repeated preamble sequence is detected on at least one said stream, said packet detector also having a RESET input for suspending packet detection while said RESET input is asserted and an SNR_MODE input for increasing the sensitivity of said packet detector when said SNR_MODE is not asserted and decreasing said packet detector sensitivity when said SNR_MODE is asserted;
• an AGC controller for each said stream of IQ receiver data, said AGC controller establishing an inter-packet gain level, said AGC controller also having a FREEZE input for suspending said gain control process;
• a signal strength detector for each said stream of IQ receiver data, said signal strength detector asserting a GT_NFLR output when the signal strength of an associated said stream of IQ receiver data increases and also asserting SNR_MODE if one or more said GT_NFLR outputs is asserted;
• said packet acquisition processor asserting said FREEZE input to all said AGC controllers if said packet detect output is asserted for any said stream of IQ receiver data.