Synchronous global controller for enhanced pipelining
AssigneeBroadcom Corporation
InventorsAli Anvar, Gil I. Winograd, Esin Terzioglu
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Abstract
The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.
Claims20
A controller adapted to generate different clock pulses for read and write operations, wherein at least one of said different clock pulses is extended wherein said at least one of said different clock pulses is a write clock pulse.
A memory device comprising:
- at least one local memory block;
- and
- a global controller coupled to at least said local memory block and adapted to manage timing of read and write operations, wherein said global controller is further adapted to extend a portion of a write clock pulse.
A method for processing read and write operations in a memory architecture having a synchronous global controller, the method comprising:
- generating control signals;
- and
- skewing at least one write clock pulse with the synchronous global controller.
A method for processing read and write operations in a memory architecture comprising skewing a clock pulse using a global controller, wherein skewing said clock pulse includes extending a high portion of said clock pulse using at least one word line interfacing with said global controller.
A controller adapted to generate different clock pulses for read and write operations, further adapted to skew at least one pre-charge signal for at least a read operation.
Dependencies are inferred from the claim text.