Memory system and method that changes voltage and frequency

A memory system comprising:

• a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage, where the semiconductor memory operates in synchronization with a clock signal;
• a first control unit that includes a control input/output circuit, which is coupled to the memory input/output circuit and operates according to the second power supply voltage, where the first control unit operates in synchronization with the clock signal;
• a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal;
• a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal;
• and
• a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory provided by the first control unit;
• wherein the voltage generating unit comprises:
• a first generating unit that outputs the second power supply voltage having a first voltage;
• a second generating unit that outputs the second power supply voltage having a second voltage;
• and
• a third generating unit that temporarily outputs the first voltage when the second power supply voltage is changed from the second voltage to the first voltage.

A method for controlling semiconductor memory which operates in synchronization with a clock signal and includes a plurality of operation modes, the method comprising:

• making an internal circuit of the semiconductor memory operate according to a first power supply voltage,
• inputting/outputting a signal to/from the internal circuit according to a second power supply voltage,
• determining an operation mode according to an access state of the semiconductor memory,
• changing at least one of the second power supply voltage and the frequency of the clock signal based on the determined operation mode;
• converting a signal level of the second power supply voltage outputted from an input buffer into a signal level of the first power supply voltage, and
• selectively coupling the output of a level shifter disposed between the input buffer and the internal circuit or the output of the input buffer to the internal circuit based on a relationship between the second power supply voltage and the first power supply voltage.