Test apparatus of semiconductor integrated circuit and method using the same
AssigneeHynix Semiconductor Inc.
InventorsJong-Sam Kim, Kwang-Jun Cho
Life of this patent
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Abstract
A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.
Claims16
A method for testing a semiconductor integrated circuit comprising:
- storing a first test code in a first test apparatus through a signal line when a first test mode signal is deactivated;
- outputting the first test code stored in the first test apparatus when the first test mode signal is activated;
- storing a second test code in a second test apparatus through a signal line when a second test signal is deactivated;
- and
- outputting the second test code stored in the second test apparatus when the second test mode signal is activated.
A test apparatus of a semiconductor integrated circuit comprising:
- a plurality of signal lines;
- a first test apparatus coupled with the plurality of signal lines, the first test apparatus configured to store first test signals, which are input through the plurality of signal lines, in response to a first test mode signal, and output first test code signals, the first test code signals being applied before the first test mode signal;
- and
- a second test apparatus coupled with the plurality of signal lines, the second test apparatus configured to store second test signals, which are input through the plurality of signal lines, in response to a second test mode signal and output second test code signals, the second test code signals being applied before the second test mode signal.
Dependencies are inferred from the claim text.