Semiconductor device capable of being tested after packaging
AssigneeSamsung Electronics Co., Ltd.
InventorsHee-Il Hong, Kang-Young Cho
Life of this patent
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Abstract
Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines.
Claims14
A semiconductor device comprising:
- a memory cell array including a plurality of memory cells;
- an external test pad connected to an internal test pad;
- an external pad connected to an internal pad;
- and
- a first connection unit connecting the internal pad and the internal test pad in a normal mode and disconnecting the internal pad and the internal test pad in a test mode, in response to a first control signal, wherein,
- a test voltage is applied to a plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in the test mode, the test voltage disables the plurality of word lines, and a ground voltage is applied to the semiconductor device via the external pad and the internal pad.
A memory system apparatus comprising:
- a memory device including a semiconductor device and a controller controlling the memory device, wherein the semiconductor device comprises:
- a memory cell array including a plurality of memory cells;
- an external test pad connected to an internal test pad;
- an external pad connected to an internal pad;
- and
- a first connection unit connecting the internal pad and the internal test pad in a normal mode and disconnecting the internal pad and the internal test pad in a test mode, in response to a first control signal, wherein,
- a test voltage is applied to a plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in the test mode, the test voltage disables the plurality of word lines, and a ground voltage is applied to the semiconductor device via the external pad and the internal pad.
A method for testing a semiconductor device, comprising the steps of:
- applying a ground voltage to the semiconductor device via an external pad and an internal pad;
- applying a test voltage to a plurality of word lines connected to a plurality of memory cells of a memory cell array, via an external test pad and an internal test pad, in a test mode, wherein the test voltage disables the plurality of word lines;
- applying the ground voltage to the plurality of word lines in a normal mode, wherein,
- a control signal received by a connection unit determines whether the semiconductor device is in the test mode or the normal mode;
- applying the test voltage to the plurality of word lines via the external test pad and the internal test pad in the test mode, if a voltage generator is disabled;
- applying a predetermined voltage to the plurality of word lines via the voltage generator in the test mode, if the voltage generator is enabled;
- and
- applying the predetermined voltage to the plurality of word lines via the voltage generator in the normal mode.
Dependencies are inferred from the claim text.