Semiconductor storage device adapted to prevent erroneous writing to non-selected memory cells

A semiconductor storage device comprising:

• a memory cell array having a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more);
• and
• a control circuit configured to control the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells,
• the control circuit being adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation.