Memory structure having volatile and non-volatile memory portions

A device, comprising:

• a fin field-effect transistor (finFET) comprising:
• a first gate configured to switchably receive a first signal that is configured to turn on the finFET;
• a second gate configured to switchably receive a second signal that is configured to turn on the finFET,
• wherein the first gate is coupled to a non-volatile memory, and
• wherein the finFET comprises a first layer comprising a gate oxide, a second layer, and a third layer comprising a gate oxide, wherein the first layer, second layer, and third layer are disposed adjacent to at least a portion of the channel and interposed between at least part of the source and at least part of the drain and interposed between at least part of the first gate.

A device, comprising:

• a fin field-effect transistor (finFET) comprising:
• a first gate coupled to a non-volatile memory portion;
• a second gate coupled to a volatile memory portion;
• and
• a fin disposed between the first gate and the second gate, wherein the fin comprises a source, a drain, a channel, and a dielectric portion that extends through a width of the fin, the dielectric portion disposed between the source and the drain and adjacent to at least part of the channel.